Wiring Diagram
Note: Q1~Q2 are NPN output channels. The wiring examples in the diagram only represent differential and single-ended connections, but do not imply that each channel is limited to the connections as shown in the diagram.
Terminal Description
| Terminal | Meaning |
| A1+/A1- | Channel 1, Phase A input terminal |
| B1+/B1- | Channel 1, Phase B input terminal |
| C1+/C1- | Channel 1, Phase C input terminal |
| L1_24V/COM1 | LATCH1 input terminal |
| A2+/A2- | Channel 2, Phase A input terminal |
| B2+/B2- | Channel 2, Phase B input terminal |
| C2+/C2- | Channel 2, Phase C input terminal |
| L2_24V/COM2 | LATCH2 input terminal |
| A1 | Channel 1, Phase A input terminal |
| B1 | Channel 1, Phase B input terminal |
| C1 | Channel 1, Phase C input terminal |
| COM3 | Channel 1 Phases A, B, and C input COM |
| A2 | Channel 2, Phase A input terminal |
| B2 | Channel 2, Phase B input terminal |
| C2 | Channel 2, Phase C input terminal |
| COM4 | Channel 2 Phases A, B, and C input COM |
| L_24V/COM5 | LATCH3 input terminal |
| L_24V/COM6 | LATCH4 input terminal |
| Q1 | Channel 1 gated output, NPN |
| Q2 | Channel 2 gated output, NPN |
| 5V/0V | 5V DC power output terminal |
RXPDO Parameter Description
| Input parameters | Data type | Meaning |
| CHx | ||
|
Frequency |
UDINT |
Current input frequency, unit: Hz. It is only accurate to a single digit, e.g., for a 10KHz measurement signal, the value displays as 10000. |
|
Counter value |
UDINT |
Current count value, with the highest bit as the sign bit (actually signed data). |
|
C Latch value |
UDINT |
Current count value latched in Phase C according to the configuration. |
| CHx Status | ||
|
Input A |
BOOL |
Phase A input |
|
Input B |
BOOL |
Phase B input |
|
Input C |
BOOL |
Phase C input |
|
Counter overflow |
BOOL |
1: Current count value overflow 0: After count value overflow, continue counting upward exceeding 5000. |
|
Counter underflow |
BOOL |
1: Current count value underflow 0: After count value underflow, continue counting downward exceeding 5000 |
|
Set counter done |
BOOL |
1: Effectively set the current count value of the counter 0: Set counter as 0 |
|
Latch C valid |
BOOL |
1: Flag bit for Phase C input latched 0: No latching performed; |
|
Gate Output Status |
BOOL |
1: Gated output valid 0: Gated output invalid |
| Others | ||
|
Latch1 |
BOOL |
1: Signal input detected on Latch1 channel 0: No signal input on Latch1 channel |
|
Latch1 valid |
BOOL |
1: Flag bit for Latch1 signal successfully latched 0: No latching performed |
|
Latch1 value |
UDINT |
Current count value latched by Latch1 signal according to the configuration |
|
Latch2 |
BOOL |
1: Signal input detected on Latch2 channel 0: No signal input on Latch2 channel |
|
Latch2 valid |
BOOL |
1: Flag bit for Latch2 signal successfully latched 0: No latching performed |
|
Latch2 value |
UDINT |
Current count value latched by Latch2 signal according to the configuration |
|
Latch3 |
BOOL |
1: Signal input detected on Latch3 channel 0: No signal input on Latch3 channel |
|
Latch3 valid |
BOOL |
1: Flag bit for Latch3 signal successfully latched 0: No latching performed |
|
Latch3 value |
UDINT |
Current count value latched by Latch3 signal according to the configuration |
|
Latch4 |
BOOL |
1: Signal input detected on Latch4 channel 0: No signal input on Latch4 channel |
TXPDO Parameter Description
| Parameters | Data type | Meaning |
| CHx | ||
| Set counter value | UDINT | Current counter value setting |
| Freq Update Time | UDINT | Frequency update time; range: 0~2.5s. The recommended set value should be at least 4~5 times larger than the input signal frequency period, unit: ms. |
| Config Data | Byte |
Bit0~Bit7 configuration for module operation mode; When Bit8 is 0, the gate selects count channel 1 for comparison output; when it is 1, the gate selects count channel 2 for comparison output. When Bit9 is 1, it enables count clear on the rising edge of Phase C. When Bit10 is 1, it enables count clear on the falling edge of Phase C. |
| Set counter | Bit | On the rising edge, set the “Set counter value” to the current “Counter value” |
| Enable latch C | Bit |
1: Latch the “Counter value” to “Latch value” on the rising edge of Phase C input Latch only once. To restart latching, set this parameter to 0 and then back to 1 (to avoid invalid abnormal latching caused by interference). |
| Clear cnt val | Bit | Clear channel count value |
| Clear flow flag | Bit | Clear channel overflow and underflow flags |
| Gate threshold0 | UDINT | Gated comparison value 0 |
| Gate threshold1 | UDINT | Gated comparison value 1 |
| Latchx Ctrl | ||
| ConfigData | Byte | Latch mode configuration |
| Enable latch extern on positive edge | Bit | 1: Latch the “Counter value” to “Latch value” on the rising edge of LatchNote: The trigger mode is set by Bit1 of ConfigData. |
| Enable latch extern on negative edge | Bit | 1: Latch the “Counter value” to “Latch value” on the falling edge of LatchNote: The trigger mode is set by Bit2 of ConfigData. |
Parameter Configuration Description (Channel)
| Operating mode | ||||
| Operating mode | Bit1 | Bit0 | ||
| AB-phase quadrature 4x frequency counting | 0 | 0 | ||
| AB-phase quadrature single frequency counting | 0 | 1 | ||
| Pulse + direction counting(A: Pulse B: Direction; Counts down when B is at high level, and counts up when B is at low level) | 1 | 0 | ||
| Working signal | ||||
| Working signal | Bit3 | Bit2 | ||
| 5V | 0 | 0 | ||
| 24V | 0 | 1 | ||
| Gated output configuration | ||||
| Gated mode | Bit6 | Bit5 | Bit4 | |
| Gated Output Mode 1 | 0 | 0 | 1 | |
| Gated Output Mode 2 | 0 | 1 | 1 | |
| Gated Output Mode 3 | 1 | 0 | 1 | |
| Gated Output Mode 4 | 1 | 1 | 1 | |
| Filtering configuration | ||||
| Filtering configuration | Bit7 | |||
| Disable filtering | 0 | |||
| Enable filtering | 1 | |||
| Selection of gated output comparison channels | ||||
| Selection of gated output comparison channels | Bit8 | |||
| Gated output selects channel 1 | 0 | |||
| Gated output selects channel 2 | 1 | |||
| Phase C clear configuration | ||||
| Phase C clear configuration | Bit10 | Bit9 | ||
| Close Phase C clear enable | 0 | 0 | ||
| Phase C rising edge clear enable | 0 | 1 | ||
| Phase C falling edge clear enable | 1 | 0 | ||
Gated Output Mode Description
Gated Output Mode 1
Compare between the comparison value and the counter upper limit:
Gated comparison value 0 < counter value < counter upper limit (i.e., 232- 1): output on the gate (i.e., Q channel).
Counter lower limit (i.e., 0) < counter value < gated comparison value 0: no output on the gate (i.e., Q channel).
Note: The value for the gated comparison value 1 must be set greater than that for the gated comparison value 0; otherwise, the output will be abnormal.
Gated Output Mode 2
Compare between the comparison value and the counter upper limit:
Gated comparison value 0 < counter value < counter upper limit (i.e., 232- 1): no output on the gate (i.e., Q channel).
Counter lower limit (i.e., 0) < counter value < gated comparison value 0: output on the gate (i.e., Q channel).
Note: The value for the gated comparison value 1 must be set greater than that for the gated comparison value 0; otherwise, the output will be abnormal.
Gated Output Mode 3
Compare between the comparison value 0 and comparison value 1:
Gated comparison value 0 < counter value < gated comparison value 1: output on the gate (i.e., Q channel).
Counter lower limit (i.e., 0) < counter value < gated comparison value 0, or gated comparison value 1 < counter value < upper limit value (i.e., 232- 1): no output on the gate (i.e., the Q channel).
Note: The value for the gated comparison value 1 must be set greater than that for the gated comparison value 0; otherwise, the output will be abnormal.
Gated Output Mode 4
Compare between the comparison value 0 and comparison value 1:
Gated comparison value 0 < counter value < gated comparison value 1: no output on the gate (i.e., Q channel).
Counter lower limit (i.e., 0) < counter value < gated comparison value 0, or gated comparison value 1 < counter value < upper limit value (i.e., 232- 1): output from the gate (i.e., Q channel).
Note: The value for the gated comparison value 1 must be set greater than that for the gated comparison value 0; otherwise, the output will be abnormal.