Wiring Diagram
Terminal Description
| Terminal | Description |
| A+,A- | CH0 acquisition voltage input terminal |
| B+,B- | CH1 acquisition voltage input terminal |
Parameter Description
The signal oversampling cycle is: Sample Cycle Time = Sync Unit Cycle Time/Oversampling Factor, with a minimum sampling cycle of 10us for sampling. Example: If the bus cycle time is 1000us and the sampling count is 100 times, then the sampling cycle is 10us. A value is sampled every 10us, requiring 100 executions. These data are accumulated and transmitted in the next bus cycle.
| Parameters | Description |
|
Operation Mode |
Selection of number of channels: 2 Channels: Select to use two channels 1 Channel: Select to use one channel (the first channel) |
|
Sync Unit Cycle Time (us) |
Cycle time, determined by the EtherCAT cycle time setting |
|
Oversampling Factor |
Oversampling parameter: sampling count per cycle, maximum 100 times. 1：1 2：2 3：4 4：5 5：8 6：10 7：16 8：20 9：25 10：32 11：40 12：50 13：64 14：80 15：100 |
|
Sample Cycle Time (us) |
Sampling cycle is determined by the relationship between EtherCAT cycle time and the number of samples |